As the frequency of VLSI circuits increases, the need to control skew in critical circuits becomes increasingly important. Two major process related components of skew are optical astigmatism and angle of implantation. Both of these effects are sensitive to gate orientation.
Optical astigmatism can cause vertical and/or horizontal lines to be imaged onto a silicon wafer less accurately than normal. The accuracy of these critical dimensions (CDs) is fundamental but obviously some variance must be tolerated. Variance in the width and/or length of the intended transistor channel dimensions ultimately affects the strength, β, (Eq. 1.4), i.e. the current carrying capability of the device (Eqs 1.2 & 1.3). This effect is becoming ever more dominant as CDs continue to approach photolithographical limits.
The second source of transistor driving strength modulation, albeit less dominant, is a result of a variance in the angle of implantation. This causes a modulation of the device threshold voltage, Vt, resulting in a change in the effective driving strength of the device.
In the prior art, several methods have been used to control skew. Two of these are:                use of long-channeled transistors        guaranteeing the same gate orientation of all critical circuits.        
The use of long-channel transistors minimizes the effects of poly CD variance reducing the percentage change in Leff (Eq. 1.6) caused by Δl. However, in order to achieve that same effective driving strength for the driver in question, the effective width, Weff (Eq. 1.5) must be increased so that the β of the device is equal to that of the minimum channel device. Long-channel drivers inherently consume more die area. For example, a 20% increase in Leff requires a 20% increase in Weff which translates to a 20% or more increase in silicon area required.
FIG. 1A illustrates a driver circuit that may be implemented with the various circuits described below. FIG. 1B illustrates one layout of the driver of FIG. 1A having a vertical orientation with parallel transistors. FIG. 1C illustrates an alternative layout with parallel transistors having a horizontal orientation. The driver may alternatively be implemented as a single large device, as shown in FIG. 1D. The device example shown has a W/L ratio of 12. FIG. 1E shows the horizontal embodiment of the single legged device. A vertical implementation may be done in the alternative.
Guaranteeing the same gate orientation for all critical transistors is another method of controlling skew. However, maintaining the same gate orientation is not always practical. For example, I/O cells are normally placed radially to form the I/O ring of a design as shown in FIG. 2. As can be seen, the same I/O library element is placed on both the top/bottom and left/right side of a die. Thus, the same gate orientation can not be maintained.
Therefore, an improved method of controlling skew would be advantageous.